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| ar0134: 1/3-inch 1.2 mp cmos digital image sensor features ? ar0134_ds rev. g pub. 6/15 en 1 ?semiconductor components industries, llc 2015, 1/3-inch 1.2 mp cmos digital image sensor with global shutter ar0134 datasheet, rev. g for the latest datasheet revision, please visit www.onsemi.com features ? on semiconductor's 3rd ge neration global shutter tec hnol ogy ? superior low-light performance ? hd video (720p60) ? video/single frame mode ? flexible row-skip modes ? on-chip ae and statistics engine ? parallel and serial output ? support for external led or flash ? auto black level calibration ?context switching applications ? scene processing ? scanning and machine vision ? 720p60 video applications general description on semiconductor's ar0134 is a 1/3-inch 1.2 mp cmos digital image sensor with an active-pixel array of 1280h x 960v. it is designed for low light perfor- mance and features a global shutter for accurate cap- ture of moving scenes. it includes sophisticated camera functions such as auto exposure control, win- dowing, scaling, row skip mode, and both video and single frame modes. it is programmable through a sim- ple two-wire serial interf ace. the ar0134 produces extraordinarily clear, sharp digital pictures, and its ability to capture both co ntinuous video and single frames makes it the perfect choice for a wide range of applications, including sc anning and industrial inspection. table 1: key parameters parameter typical value optical format 1/3-inch (6 mm) active pixels 1280h x 960v = 1.2 mp pixel size 3.75 ? m color filter array rgb bayer or monochrome shutter type global shutter input clock range 6 C 50 mhz output pixel clock (maximum ) 74.25 mhz output serial hispi parallel 12-bit frame rate full resolution 54 fps 720p 60 fps responsivity monochrome 6.1 v/lux-sec color 5.3 v/lux-sec snr max 38.6 db dynamic range 64 db supply voltage i/o 1.8 or 2.8 v digital 1.8 v analog 2.8 v hispi 0.4 v power consumption <400 mw operating temperature C30c to +70c (ambient) C30c to +80c ( junction) package options 9 x 9 mm 64-pin ibga 10 x 10 mm 48-pin ilcc bare die
ar0134_ds rev. g pub. 6/15 en 2 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor ordering information ordering information see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit ou r web site at www.onsemi.com. table 2: available part numbers part number product description orderable product attribute description ar0134cssc00spca0-dpbr color, ilcc (parallel) dry pack with protective film, double side bbar glass ar0134cssc00spca0-drbr color, ilcc (parallel) dry pack without protective film, double side bbar glass ar0134cssc00spca0-tpbr color, ilcc (parallel) tape & reel with protective film, double side bbar glass ar0134cssc00spca0-trbr color, ilcc (parallel) tape & re el without protective film, double side bbar glass ar0134cssc00spcad-gevk color, ilcc (parallel), demo kit ar0134cssc00spcah-gevb color, ilcc (parallel), head board ar0134cssc00suea0-dpbr color, ibga dry pack with protective film, double side bbar glass ar0134cssc00suea0-drbr color, ibga dry pack with out protective film, double side bbar glass ar0134cssc00suea0-tpbr color, ibga tape & reel with protective film, double side bbar glass ar0134cssc00suea0-trbr color, ibga tape & reel wi thout protective film, double side bbar glass ar0134cssc00suead3-gevk color, ibga demo3 kit ar0134cssc00suead-gevk color, ibga demo kit AR0134CSSC00SUEAH-GEVB color, ibga head board ar0134cssc25suea0-dpbr color, ibga, 25deg shift dry pa ck with protective film, double side bbar glass ar0134cssc25suea0-drbr color, ibga, 25deg shift dry pack without protective film, double side bbar glass ar0134cssc25suea0-tpbr color, ibga, 25deg shift tape & re el with protective film, double side bbar glass ar0134cssc25suea0-trbr color, ibga, 25deg shift tape & re el without protective film, double side bbar glass ar0134cssm00spca0-dpbr mono, dry pack with protective film, double side bbar glass ar0134cssm00spca0-drbr mono, ilcc (parallel) dry pack without protective film, double side bbar glass ar0134cssm00spca0-tpbr mono, ilcc (parallel) tape & reel with protective film, double side bbar glass ar0134cssm00spca0-trbr mono, ilcc (parallel) tape & reel without protective film, double side bbar glass ar0134cssm00spcad-gevk mono, ilcc (parallel) demo kit ar0134cssm00spcah-gevb mono, il cc (parallel) head board ar0134cssm00suea0-dpbr mono, ibga dry pack with protective film, double side bbar glass ar0134cssm00suea0-drbr mono, ibga dry pack withou t protective film, double side bbar glass ar0134cssm00suea0-tpbr mono, ibga tape & reel with protective film, double side bbar glass ar0134cssm00suea0-trbr mono, ibga tape & reel with out protective film, double side bbar glass ar0134cssm00suead3-gevk mono, ibga, demo3 kit ar0134cssm00suead-gevk mono, ibga, demo kit ar0134cssm00sueah-gevb mono, ibga, head board ar0134cssm25spca0-drbr mono, ilcc (parallel), 25deg shift ar0134cssm25spca0-tpbr mono, ilcc (parallel), 25deg shift tap e & reel with protective film, double side bbar glass ar0134cssm25suea0-dpbr mono, ibga, head board dry pack with protective film, double side bbar glass ar0134cssm25suea0-drbr mono, ibga, 25deg shift dry pack without protective film, double side bbar glass ar0134cssm25suea0-tpbr mono, ibga, 25deg shift tape & re el with protective film, double side bbar glass ar0134cssm25suea0-trbr mono, ibga, 25deg shift tape & reel without protective film, double side bbar glass ar0134cssm25suead3-gevk mono, ibga, 25deg shift ar0134cssm25suead-gevk mono, ibga, 25deg shift demo kit ar0134cssm25sueah-gevb mono, ibga, 25deg shift head board ar0134_ds rev. g pub. 6/15 en 3 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 features overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 configuration and pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 two-wire serial register interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 power-on reset and standby timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 ar0134_ds rev. g pub. 6/15 en 4 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor list of figures list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 3: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: typical configuration: serial fo ur-lane hispi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 5: typical configuration: parallel pixel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: 9x9mm 63-ball ibga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 7: 48 ilcc package, parallel output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 8: single read from random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 9: single read from current locati on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 10: sequential read, start from rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 11: sequential read, start from curre nt location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 12: single write to random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 13: sequential write, start at rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 14: two-wire serial bus timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 15: i/o timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 16: differential output voltage for clock or data pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 17: eye diagram for clock and data signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 18: skew within the phy and output channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 19: power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 20: power down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 21: enter standby timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 22: exit standby timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 23: quantum efficiency ? monochrome sensor (typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 24: quantum efficiency ? color sens or (typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 25: 63-ball ibga package outline dr awing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 26: 48-pin ilcc package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 ar0134_ds rev. g pub. 6/15 en 5 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor list of tables list of tables table 1: key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: pin descriptions - 63-ball ibga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 4: pin descriptions - 48 ilcc package, parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 5: two-wire serial bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 6: i/o timing characterist ics, parallel output (1.8v v dd _io) 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 7: i/o timing characterist ics, parallel output (2.8v v dd _io) 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 8: i/o rise slew rate (2.8v v dd _io) 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 9: i/o fall slew rate (2.8v v dd _io) 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 10: i/o rise slew rate (1.8v v dd _io) 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 11: i/o fall slew rate (1.8v v dd _io) 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 12: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 13: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 14: operating current consumption for parallel output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 15: standby current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 16: input voltage and current (hispi power supply 0.4 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 17: rise and fall times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 18: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 19: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 20: chief ray angle - 25deg mono . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 ar0134_ds rev. g pub. 6/15 en 6 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor general description general description the on semiconductor ar0134 can be operated in its default mode or programmed for frame size, exposure, gain, and other paramete rs. the default mode output is a full-reso- lution image at 54 frames per second (fps). it outputs 12-bit raw data, using either the parallel or serial (hispi) output ports. the device may be operated in video (master) mode or in frame trigger mode. frame_valid and line_valid signals are output on dedicated pins, along with a synchronized pixel clock. a dedicated flash pin can be programmed to control external led or flash exposure illumination. the ar0134 includes additional features to allow application-specific tuning: windowing, adjustable auto-exposure contro l, auto black level correction, on-board temperature sensor, and row sk ip and digital binning modes. the sensor is designed to operate in a wide temperature range (?30c to +70c). functional overview the ar0134 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 50 mhz. the maximum output pixel rate is 74.25 mp/s, corresponding to a clock rate of 74.25 mhz. figure 1 shows a block diagram of the sensor. figure 1: block diagram user interaction with the sensor is through the two-wire serial bus, which communi- cates with the array control, analog signal chai n, and digital signal chain. the core of the sensor is a 1.2 mp active- pixel sensor arra y. the ar0134 features global shutter tech- nology for accurate capture of moving images. the exposure of the entire array is controlled by programming the integration time by register setting. all rows simultane- ously integrate light prior to readout. once a row has been read, the data from the columns is sequenced through an analog sign al chain (providing offset correction and gain), and then through an analog-to- digita l converter (adc). the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital control registers active pixel sensor (aps) array pll memory otpm temperature sensor timing and control (sequencer) analog processing and a/d conversion auto exposure and stats engine pixel data path (signal processing) external clock serial output flash parallel output two-wire serial interface trigger power ar0134_ds rev. g pub. 6/15 en 7 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor features overview processing signal chain (which provides furt her data path corrections and applies digital gain). the pixel data are output at a rate of up to 74.25 mp/s, in parallel to frame and line synchronization signals. features overview the ar0134 global sensor shutter has a wide array of features to enhance functionality and to increase versatility. a summary of fe atures follows. please refer to the ar0134 developer guide for detailed feature descriptions, register settings, and tuning guide- lines and recommendations. ?operating modes the ar0134 works in master (video), trigger (single frame), or auto trigger modes. in master mode, the sensor generates the in tegration and readout timing. in trigger mode, it accepts an external trigger to start exposure, then generates the exposure and readout timing. the exposure time is prog rammed through the two-wire serial inter- face for both modes. trigger mode is not compatible with the hispi interface. ?window control configurable window size and blanking ti mes allow a wide range of resolutions and frame rates. digital binning and skipping modes are supported, as are vertical and horizontal mirror operations. ?context switching context switching may be used to rapidly switch between two sets of register values. refer to the ar0134 developer guide for a complete set of context switchable regis- ters. ?gain the ar0134 global shutter sensor can be conf igured for analog gain of up to 8x, and digital gain of up to 8x. ?automatic exposure control the integrated automatic exposure control may be used to ensure optimal settings of exposure and gain are computed and update d every other frame. refer to the ar0134 developer guide for more details. ?hispi the ar0134 global shutter image sensor supports two or three lanes of streaming-sp or packetized-sp protocols of on semiconduc tor's high-speed serial pixel interface. ?pll an on chip pll provides reference clock flexibility and supports spread spectrum sources for improved emi performance. ?reset the ar0134 may be reset by a register write, or by a dedicated input pin. ?output enable the ar0134 output pins may be tri-stated using a dedicated output enable pin. ?temperature sensor the temperature sensor is only guaranteed to be functional when the ar0134 is initially powered-up or is reset at temperatures at or above 0c. ? black level correction ?row noise correction ? column correction ? test patterns several test patterns may be enabled for debug purposes. these include a solid color, color bar, fade to grey, and a walking 1s test pattern. ar0134_ds rev. g pub. 6/15 en 8 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor pixel data format pixel data format pixel array structure the ar0134 pixel array is configured as 1412 columns by 1028 rows, (see figure 2). the dark pixels are optically black and are used internally to monitor black level. of the right 108 columns, 64 are dark pixels used for row noise correction. of the top 24 rows of pixels, 12 of the dark rows are used for black level correction. there are 1296 columns by 976 rows of optically active pixels. while the sensor's format is 1280 x 960, the additional active columns and active rows are included fo r use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. the pixel adjustment is always performed for monochrome or color versions. the active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. not all dummy pixels or barrier pixels can be read out. figure 2: pixel array description 2 light dummy + 4 barrier + 24 dark + 4 barrier + 6 dark dummy dark pixel barrier pixel light dummy pixel active pixel 2 light dummy + 4 barrier + 6 dark dummy 1412 2 light dummy + 4 barrier 2 light dummy + 4 barrier + 100 dark + 4 barrier 1028 1296 x 976 (1288 x 968 active) 4.86 x 3.66 mm 2 (4.83 x 3.63 mm 2 ) ar0134_ds rev. g pub. 6/15 en 9 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor pixel data format figure 3: pixel color pattern detail (top right corner) default readout order by convention, the sensor core pixel array is shown with the first addressable (logical) pixel (0,0) in the top right corner (see figure 3). this reflects the actual layout of the array on the die. also, the physical location of the first pixel data read out of the sensor in default condition is that of pixel (112, 44). active pixel (0,0) array pixel (110, 40) row reado ut direction g b g b g b r g r g r g r g r g r g r g r g r g r g r g r g g b g b g b g b g b g b g b g b g b column readout direction ar0134_ds rev. g pub. 6/15 en 10 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor configuration and pinout configuration and pinout the figures and tables below show a typical configuration for the ar0134 image sensor and show the package pinouts. figure 4: typical configuration: serial four-lane hispi interface notes: 1. all power supplies mu st be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but it may be greater for slower two-wire speed. 3. this pull-up resistor is not required if the contro ller drives a valid logic level on sclk at all times. 4. the parallel interface output pads can be left un connected if the serial output interface is used. 5. on semiconductor recommends that 0.1f and 10f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- out and design considerations. refer to the ar0 134 demo headboard schema tics for circuit recom- mendations. 6. on semiconductor recommends that analog powe r planes be placed in a manner such that cou- pling with the digital power planes is minimized. 7. although 4 serial lanes are shown, the ar0134 supports only 2 or 3 lane hispi. v dd _io v dd _slvs v dd _pll v dd v aa v dd v aa v aa _pix master clock (6C50 mhz) s data s clk reset_bar test extclk d gnd a gnd digital ground analog ground digital core power 1 hispi power 1 analog power 1 to controller from controller v dd _io v dd _pll pll power 1 digital i/o power 1 1.5k 2 1.5k 2, 3 analog power 1 v aa _pix slvsc_n slvsc_p slvs0_p slvs0_n slvs1_p slvs1_n slvs2_p slvs2_n slvs3_p 7 slvs3_n 7 flash v dd _slvs oe_bar standby ar0134_ds rev. g pub. 6/15 en 11 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor configuration and pinout figure 5: typical configuration: parallel pixel data interface notes: 1. all power supplies mu st be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but it may be greater for slower two-wire speed. 3. this pull-up resistor is not required if the contro ller drives a valid logic level on sclk at all times. 4. the serial interface output pads can be left un connected if the parallel ou tput interface is used. 5. on semiconductor recommends that 0.1f and 10f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- out and design considerations. refer to the ar0 134 demo headboard schema tics for circuit recom- mendations. 6. on semiconductor recommends that analog powe r planes be placed in a manner such that cou- pling with the digital power planes is minimized. v dd master clock (6C50 mhz) s data s clk test flash frame_valid d out [11:0] extclk d gnd digital ground analog ground digital core power 1 to controller from controller line_valid pixclk reset_bar v dd _io digital i/o power 1 1.5k 2 1.5k 2, 3 v aa vaa_pix analog power 1 vdd_pll pll power 1 analog power 1 vaa_pix v dd _io v dd _pll v dd v aa trigger oe_bar standby a gnd ar0134_ds rev. g pub. 6/15 en 12 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor configuration and pinout figure 6: 9x9mm 63-ball ibga package a b c d e f g h top view (ball down) slvs0n slvs0p slvs1n slvs1p v dd standby v dd _pll slvscn slvscp slvs2n slvs2p v dd v aa v aa extclk v dd _ slvs (slvs3n) (slvs3p) d gnd v dd a gnd a gnd s addr sclk s data d gnd d gnd v dd v aa _pix v aa _pix line_ valid frame_ valid pixclk flash d gnd v dd _io reserved d out 8 d out 9d out 10 d out 11 d gnd test d out 4 d out 5d out 6d out 7 d gnd trigger oe_bar d out 0 d out 1 d out 2d out 3d gnd reset _bar 12 3 567 8 4 v dd v dd _io v dd _io v dd _io v dd _io reserved reserved ar0134_ds rev. g pub. 6/15 en 13 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor configuration and pinout table 3: pin descriptions - 63-ball ibga package name ibga pin type description slvs0_n a2 output hispi serial data, lane 0, differential n. slvs0_p a3 output hispi serial data, lane 0, differential p. slvs1_n a4 output hispi serial data, lane 1, differential n. slvs1_p a5 output hispi serial data, lane 1, differential p. standby a8 input standby-mode enable pin (active high). vdd_pll b1 power pll power. slvsc_n b2 output hispi serial ddr clock differential n. slvsc_p b3 output hispi serial ddr clock differential p. slvs2_n b4 output hispi serial data, lane 2, differential n. slvs2_p b5 output hispi serial data, lane 2, differential p. v aa b7, b8 power analog power. extclk c1 input external input clock. v dd _slvs c2 power hispi power. (may leave unco nnected if parallel interface is used) slvs3_n c3 output (unsupported) hispi serial data, lane 3, differential n. slvs3_p c4 output (unsupported) hispi serial data, lane 3, differential p. d gnd c5, d4, d5, e5, f5, g5, h5 power digital gnd. v dd a6, a7, b6, c6, d6 power digital power. a gnd c7, c8 power analog gnd. s addr d1 input two-wire serial address select. s clk d2 input two-wire serial clock input. s data d3 i/o two-wire serial data i/o. v aa _pix d7, d8 power pixel power. line_valid e1 output asserted when d out line data is valid. frame_valid e2 output asserted when d out frame data is valid. pixclk e3 output pixel clock out. d out is valid on rising edge of this clock. flash e4 output control signal to drive external light sources. v dd _io e6, f6, g6, h6, h7 power i/o supply power. d out 8 f1 output parallel pixel data output. d out 9 f2 output parallel pixel data output. d out 10 f3 output parallel pixel data output. d out 11 f4 output parallel pixel data output (msb) test f7 input manufacturing test enable pin (connect to d gnd ). d out 4 g1 output parallel pixel data output. d out 5 g2 output parallel pixel data output. d out 6 g3 output parallel pixel data output. d out 7 g4 output parallel pixel data output. trigger g7 input exposure synchronization input. (connect to d gnd if hispi interface is used) oe_bar g8 input output enable (active low). d out 0 h1 output parallel pixel data output (lsb) d out 1 h2 output parallel pixel data output. d out 2 h3 output parallel pixel data output. d out 3 h4 output parallel pixel data output. ar0134_ds rev. g pub. 6/15 en 14 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor configuration and pinout figure 7: 48 ilcc package, parallel output reset_bar h8 input asynchronous reset (active low). all settings are restored to factory default. reserved e7, e8, f8 n/a reserved (do not connect). table 3: pin descriptions (continued)- 63-ball ibga package name ibga pin type description 6 5 4 3 2 1 48 47 46 45 44 43 d gnd extclk v dd _p ll d out 6 d gnd nc 7 d out 7 nc 42 8 d out 8 nc 41 9 d out 9 v aa 40 10 d out 10 a gnd 39 11 d out 11 v aa _pix 38 12 v dd _io v aa _pix 37 13 pixclk v aa 36 14 v dd a gnd 35 15 s clk v aa 34 16 s data reserved 33 17 reset _bar reserved 32 18 v dd _io reserved 31 v dd nc nc standby s addr test flash trigger frame_valid line_valid d gnd 19 20 21 22 23 24 25 26 27 28 29 30 d out 5 d out 4 d out 3 d out 2 d out 1 d out 0 oe_bar ar0134_ds rev. g pub. 6/15 en 15 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor configuration and pinout table 4: pin descriptions - 48 ilcc package, parallel pin number name type description 1d out 4 output parallel pixel data output. 2d out 5 output parallel pixel data output. 3d out 6 output parallel pixel data output. 4v dd _pll power pll power. 5 extclk input external input clock. 6d gnd power digital ground. 7d out 7 output parallel pixel data output. 8d out 8 output parallel pixel data output. 9d out 9 output parallel pixel data output. 10 d out 10 output parallel pixel data output. 11 d out 11 output parallel pixel data output (msb). 12 v dd _io power i/o supply power. 13 pixclk output pixel clock out. d out is valid on rising edge of this clock. 14 v dd power digital power. 15 s clk input two-wire serial clock input. 16 s data i/o two-wire serial data i/o. 17 reset_bar input asynchronous reset (active low). all settings are restored to factory default. 18 v dd _io power i/o supply power. 19 v dd power digital power. 20 nc no connection. 21 nc no connection. 22 standby input standby-mode enable pin (active high). 23 oe_bar input output enable (active low). 24 s addr input two-wire serial address select. 25 test input manufacturing test enable pin (connect to d gnd ). 26 flash output flash output control. 27 trigger input exposure synchronization input. 28 frame_valid output asserted when d out frame data is valid. 29 line_valid output asserted when d out line data is valid. 30 d gnd power digital ground 31 reserved n/a reserved (do not connect). 32 reserved n/a reserved (do not connect). 33 reserved n/a reserved (do not connect). 34 v aa power analog power. 35 a gnd power analog ground. 36 v aa power analog power. 37 v aa _pix power pixel power. 38 v aa _pix power pixel power. 39 a gnd power analog ground. 40 v aa power analog power. 41 nc no connection. 42 nc no connection. 43 nc no connection. ar0134_ds rev. g pub. 6/15 en 16 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor configuration and pinout 44 d gnd power digital ground. 45 d out 0 output parallel pixel data output (lsb) 46 d out 1 output parallel pixel data output. 47 d out 2 output parallel pixel data output. 48 d out 3 output parallel pixel data output. table 4: pin descriptions (continued)- 48 ilcc package, parallel pin number name type description ar0134_ds rev. g pub. 6/15 en 17 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor two-wire serial register interface two-wire serial register interface the two-wire serial interface bus enables read /write access to control and status regis- ters within the ar0134.the interface protoc ol uses a master/slave model in which a master controls one or more slave devices. th e sensor acts as a slave device. the master generates a clock (s clk ) that is an input to the sensor and is used to synchronize trans- fers. data is transferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd _io off-chip by a 1.5k ? resistor. either the slave or master device can drive s data low?the interface protocol determines which device is allowed to drive s data at any given time. the protocols described in the two-wire seri al interface specific ation allow the slave device to drive s clk low; the ar0134 uses s clk as an input only and therefore never drives it low. protocol data transfers on the two-wire serial interf ace bus are performed by a sequence of low- level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition the bus is idle when both s clk and s data are high. control of the bus is initiated with a start condition, and the bus is released wi th a stop condition. only the master can generate the start and stop conditions. start condition a start condition is defined as a high-to-low transition on s data while sc lk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop cond ition; this is known as a ?repeated start? or ?restart? condition. stop condition a stop condition is defined as a low-to-high transition on s data while sc lk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/da ta direction byte and for message bytes. one data bit is transferred during each s clk clock period. s data can change when sc lk is low and must be stable while sc lk is high. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the ar0134 are 0x20 (write address) and 0x21 (read address) in accordance with the specificatio n. alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the s addr input. ar0134_ds rev. g pub. 6/15 en 18 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor two-wire serial register interface an alternate slave address can al so be programmed through r0x31fc. message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the sc lk clock period following the data transfer. the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. as for data transfers, s data can change when sc lk is low and must be stable while sc lk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the sc lk clock period following a data transfer. a no-acknowledge bit is used to terminate a read sequence. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indi- cates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowl- edge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which the write should take place. this transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequ ence to indicate that the byte has been received. the master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence . the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same wa y as with a write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the slave?s inte rnal register address is automatically incre- mented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowledge bit. ar0134_ds rev. g pub. 6/15 en 19 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor two-wire serial register interface single read from random location this sequence (figure 8 on page 19) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates the write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. the master terminates the read by generating a no- acknowledge bit followed by a stop condition. figure 8 shows how the internal register address maintained by the ar0134 is loaded and incremented as the sequence proceeds. figure 8: single read from random location single read from current location this sequence (figure 9) performs a read using the current value of the ar0134 internal register address. the master terminates th e read by generating a no-acknowledge bit followed by a stop condition. the figure shows two independent read sequences. figure 9: single read from current location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+1 a slave address 1 s a read data slave address a 1 s p read data p previous reg address, n reg address, n+1 n+2 a a ar0134_ds rev. g pub. 6/15 en 20 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor two-wire serial register interface sequential read, start from random location this sequence (figure 10) starts in the same way as the single read from random loca- tion (figure 8). instead of generating a no-ackno wledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 10: sequential read, start from random location sequential read, start from current location this sequence (figure 11) starts in the same way as the single read from current loca- tion (figure 9 on page 19). instead of generati ng a no-acknowledge bit after the first byte of data has been transferred, the master gen erates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 11: sequential read, start from current location single write to random location this sequence (figure 12) begins with the ma ster generating a start condition. the slave address/data direction byte signals a writ e and is followed by the high then low bytes of the register address that is to be writ ten. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 12: single write to random location slave address 0 s sr a reg address[15:8] a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a 1 m+l-2 m+l-1 m+l a read data read data previous reg address, n n+1 n+2 n+l-1 n+l read data slave address a 1 read data a p s a a a slave address 0 s a reg address[15:8] a reg address[7:0] a p previous reg address, n reg address, m m+ 1 a a write data ar0134_ds rev. g pub. 6/15 en 21 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor two-wire serial register interface sequential write, start at random location this sequence (figure 13) starts in the same way as the single write to random location (figure 12). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been written. the writ e is terminated by the master generating a st op condition. figure 13: sequential write, start at random location slave address 0 s a reg address[15:8] a a reg address[7:0] a previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a m+l-2 m+l-1 m+l a a p write data write data write data write data write data ar0134_ds rev. g pub. 6/15 en 22 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor electrical specifications electrical specifications unless otherwise stated, the following specif ications apply to the following conditions: v dd = 1.8v ? 0.10/+0.15; v dd _io = v dd _pll = v aa = v aa _pix = 2.8v 0.3v; v dd _slvs = 0.4v ? 0.1/+0.2; t a = -30 c to +70 c; output load = 10pf; pixclk frequency = 74.25 mhz; hispi off. two-wire serial register interface the electrical characteristics of the two-wire serial register interface (s clk , s data ) are shown in figure 14 and table 5. figure 14: two-wire serial bus timing parameters note: read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. table 5: two-wire serial bus characteristics f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _dac = 2.8v; t a = 25c parameter symbol standard-mode fast-mode unit min max min max s clk clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - ? s low period of the sclk clock t low 4.7 - 1.3 - ? s high period of the sclk clock t high 4.0 - 0.6 - ? s set-up time for a repeated start condition t su;sta 4.7 - 0.6 - ? s data hold time: t hd;dat 0 4 3.45 5 0 6 0.9 5 ? s data set-up time t su;dat 250 - 100 6 -ns rise time of both s data and s clk signals t r - 1000 20 + 0.1cb 7 300 ns fall time of both s data and s clk signals t f - 300 20 + 0.1cb 7 300 ns s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f s data s clk p s t buf t r t f t r t hd;sta ar0134_ds rev. g pub. 6/15 en 23 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor electrical specifications notes: 1. this table is based on i 2 c standard (v2.1 january 2000). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd and v ilmax = 0.1v dd levels. sensor exclk = 27 mhz. 4. a device must internally provide a hold time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the device does not stretch the low period ( t low) of the s clk signal. 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automa tically be the case if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the s clk line is released. 7. cb = total capacitance of one bus line in pf. set-up time for stop condition t su;sto 4.0 - 0.6 - ? s bus free time between a stop and start condition t buf 4.7 - 1.3 - ? s capacitive load for each bus line cb - 400 - 400 pf serial interface input pin capacitance cin_si - 3.3 - 3.3 pf s data max load capacitance cload_sd - 30 - 30 pf s data pull-up resistor rsd 1.5 4.7 1.5 4.7 k ? table 5: two-wire serial bus characteristics f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _dac = 2.8v; t a = 25c parameter symbol standard-mode fast-mode unit min max min max ar0134_ds rev. g pub. 6/15 en 24 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor electrical specifications i/o timing by default, the ar0134 launches pixel data, fv and lv with the falling edge of pixclk. the expectation is that the user captures d out [11:0], fv and lv using the rising edge of pixclk. the launch edge of pixclk can be configured in register r0x3028. see figure 15 and table 6 for i/o timing (ac) characteristics. figure 15: i/o timing diagram table 6: i/o timing characteristics, parallel output (1.8v v dd _io) 1 symbol definition condition min typ max unit f extclk input clock frequency 650mhz t extclk input clock period 20 166 ns t r input clock rise time pll enabled 3ns t f input clock fall time pll enabled 3ns t jjitter input clock jitter 600 ns t cp extclk to pixclk propagation delay nominal voltages, pll disabled, pixclk slew rate = 4 5.7 14.3 ns t rp pixclk rise time pclk slew rate = 6 1.3 4.0 ns t fp pixclk fall time pclk slew rate = 6 1.3 3.9 ns pixclk duty cycle 40 50 60 % f pixclk pixclk frequency pixclk slew rate = 6, data slew rate = 7 6 74.25 mhz t pd pixclk to data valid pixclk slew rate = 6, data slew rate = 7 -2.5 2 ns t pfh pixclk to fv high pixclk slew rate = 6, data slew rate = 7 -2.5 2 ns t plh pixclk to lv high pixclk slew rate = 6, data slew rate = 7 -3 1.5 ns t pfl pixclk to fv low pixclk slew rate = 6, data slew rate = 7 -2.5 2 ns t pll pixclk to lv low pixclk slew rate = 6, data slew rate = 7 -3 1.5 ns c in input pin capacitance 2.5 pf data[11:0] line_valid/ pixclk extclk t r t extclk t f frame_valid leads line_valid by 6 pixclks. frame_valid trails line_valid by 6 pixclks. t plh t pfh t pfl t pll t pd pxl _0 pxl _1 pxl _2 pxl _n 90% 10% t rp t fp 90% 10% frame_valid ar0134_ds rev. g pub. 6/15 en 25 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor electrical specifications notes: 1. minimum and maximum values are taken at 70 c, 1.7v and -30 c, 1.95v. all values are taken at the 50% transition point. the loading used is 10 pf. 2. jitter from pixclk is already taken into accoun t in the data for all of the output parameters. notes: 1. minimum and maximum values are taken at 70 c, 1.7v and -30 c, 1.95v. all values are taken at the 50% transition point. the loading used is 10 pf. 2. jitter from pixclk is already taken into accoun t in the data for all of the output parameters. table 7: i/o timing characteristics, parallel output (2.8v v dd _io) 1 symbol definition condition min typ max unit f extclk input clock frequency 650mhz t extclk input clock period 20 166 ns t r input clock rise time pll enabled 3ns t f input clock fall time pll enabled 3ns t jjitter input clock jitter 600 ns t cp extclk to pixclk propagation delay nominal voltages, pll disabled, pixclk slew rate = 4 5.3 13.4 ns t rp pixclk rise time pclk slew rate = 6 1.3 4.0 ns t fp pixclk fall time pclk slew rate = 6 1.3 3.9 ns pixclk duty cycle 40 50 60 % f pixclk pixclk frequency pixclk slew rate = 6, data slew rate = 7 674.25mhz t pd pixclk to data valid pixclk slew rate = 6, data slew rate = 7 -2.5 2 ns t pfh pixclk to fv high pixclk slew rate = 6, data slew rate = 7 -2.5 2 ns t plh pixclk to lv high pixclk slew rate = 6, data slew rate = 7 -2.5 2 ns t pfl pixclk to fv low pixclk slew rate = 6, data slew rate = 7 -2.5 2 ns t pll pixclk to lv low pixclk slew rate = 6, data slew rate = 7 -2.5 2 ns c in input pin capacitance 2.5 pf ar0134_ds rev. g pub. 6/15 en 26 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor electrical specifications note: 1. minimum and maximum values are taken at 70 c, 2.5v and -30 c, 3.1v. the loading used is 10 pf. note: 1. minimum and maximum values are taken at 70 c, 2.5v and -30 c, 3.1v. the loading used is 10 pf. table 8: i/o rise slew rate (2.8v v dd _io) 1 parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 1.50 2.50 3.90 v/ns 6 default 0.98 1.62 2.52 v/ns 5 default 0.71 1.12 1.79 v/ns 4 default 0.52 0.82 1.26 v/ns 3 default 0.37 0.58 0.88 v/ns 2 default 0.26 0.40 0.61 v/ns 1 default 0.17 0.27 0.40 v/ns 0 default 0.10 0.16 0.23 v/ns table 9: i/o fall slew rate (2.8v v dd _io) 1 parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 1.40 2.30 3.50 v/ns 6 default 0.97 1.61 2.48 v/ns 5 default 0.73 1.21 1.86 v/ns 4 default 0.54 0.88 1.36 v/ns 3 default 0.39 0.63 0.88 v/ns 2 default 0.27 0.43 0.66 v/ns 1 default 0.18 0.29 0.44 v/ns 0 default 0.11 0.17 0.25 v/ns ar0134_ds rev. g pub. 6/15 en 27 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor electrical specifications note: 1. minimum and maximum values are taken at 70 c, 1,7v and -30 c, 1.95v. the loading used is 10 pf. notes: 1. minimum and maximum values are taken at 70 c, 1.7v and -30 c, 1.95v. the loading used is 10 pf. table 10: i/o rise slew rate (1.8v v dd _io) 1 parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 0.57 0.91 1.55 v/ns 6 default 0.39 0.61 1.02 v/ns 5 default 0.29 0.46 0.75 v/ns 4 default 0.22 0.34 0.54 v/ns 3 default 0.16 0.24 0.39 v/ns 2 default 0.12 0.17 0.27 v/ns 1 default 0.08 0.11 0.18 v/ns 0 default 0.05 0.07 0.10 v/ns table 11: i/o fall slew rate (1.8v v dd _io) 1 parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 0.57 0.92 1.55 v/ns 6 default 0.40 0.64 1.08 v/ns 5 default 0.31 0.50 0.82 v/ns 4 default 0.24 0.38 0.61 v/ns 3 default 0.18 0.27 0.44 v/ns 2 default 0.13 0.19 0.31 v/ns 1 default 0.09 0.13 0.20 v/ns 0 default 0.05 0.08 0.12 v/ns ar0134_ds rev. g pub. 6/15 en 28 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor electrical specifications dc electrical characteristics the dc electrical characteristics are show n in table 12, table 13, table 14, and table 15. caution stresses greater than those listed in table 13 may cause permanent damage to the device. this is a stress rating only, and functional ope ration of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. note: 1. exposure to absolute maximum rating condit ions for extended periods may affect reliability. table 12: dc electrical characteristics symbol definition condition min typ max unit v dd core digital voltage 1.7 1.8 1.95 v v dd _io i/o digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 v v aa analog voltage 2.5 2.8 3.1 v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v dd _pll pll supply voltage 2.5 2.8 3.1 v v dd _slvs hispi supply voltage 0.3 0.4 0.6 v v ih input high voltage v dd _io * 0.7 C C v v il input low voltage CCv dd _io * 0.3 v i in input leakage current no pull-up resistor; v in = v dd _io or d gnd 20 C C ? a v oh output high voltage v dd _io C 0.3 C C v v ol output low voltage v dd _io = 2.8v C C 0.4 v i oh output high current at specified v oh C22 C C ma i ol output low current at specified v ol CC22ma table 13: absolute maximum ratings symbol parameter minimum maximum unit symbol v supply power supply voltage (all supplies) C0.3 4.5 v v supply i supply total power supply current C 200 ma i supply i gnd total ground current C 200 ma i gnd v in dc input voltage C0.3 v dd _io + 0.3 v v in v out dc output voltage C0.3 v dd _io + 0.3 v v out t stg 1 storage temperature C40 +85 c t stg 1 table 14: operating current consumption for parallel output v aa = v aa _pix = v dd _io = v dd _pll = 2.8v; v dd = 1.8v; pll enabled and pixclk = 74.25 mhz; t a = 25c; c load = 10pf condition symbol min typ max unit digital operating current parallel, streaming, full resolution 54 fps i dd 14660ma i/o digital operating current parallel, streaming, full resolution 54 fps i dd _io 52 C ma analog operating current parallel, streaming, full resolution 54 fps i aa 46 55 ma pixel supply current parallel, streaming, full resolution 54 fps i aa _pix 7 9 ma pll supply current parallel, stre aming, full resolution 54 fps i dd _pll 8 10 ma ar0134_ds rev. g pub. 6/15 en 29 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor electrical specifications hispi electrical specifications the on semiconductor ar0134 sensor supports slvs mode only, and does not have a dll for timing adjustments. refer to the high -speed serial pixel (h ispi) interface phys- ical layer specification v2.00.00 for electric al definitions, specifications, and timing information. the v dd _slvs supply in this data sheet corresponds to v dd _tx in the hispi physical layer specification. similarly, v dd is equivalent to v dd _hispi as refer- enced in the specification. the hispi transmi tter electrical specifications are listed at 700 mhz. table 15: standby current consumption analog - v aa + v aa _pix + v dd _pll; digital - v dd + v dd _io; t a = 25c definition condition min typ max unit hard standby (clock off, driven low) analog, 2.8v C 3 15 ? a digital, 1.8v C 25 80 ? a hard standby (clock on, extclk = 20 mhz) analog, 2.8v C 12 25 ? a digital, 1.8v C 1.1 1.7 ma soft standby (clock off, driven low) analog, 2.8v C 3 15 ? a digital, 1.8v C 25 80 ? a soft standby (clock on, extclk = 20 mhz) analog, 2.8v C 12 25 ? a digital, 1.8v C 1.1 1.7 ma table 16: input voltage and current (hispi power supply 0.4 v) measurement conditions: max freq 700 mhz parameter symbol min typ max unit supply current ( pwr hispi) (driving 100 ? load) i dd _slvs C 10 15 ma hispi common mode voltage (driving 100 ? load) v cmd v dd _slvs x 0.45 v dd _slvs/2 v dd _slvs x 0.55 v hispi differential output voltage (driving 100 ? load) |v od |v dd _slvs x 0.36 v dd _slvs/2 v dd _slvs x 0.64 v change in v cm between logic 1 and 0 ? v cm 25 mv change in |v od | between logic 1 and 0 |v od |25mv vod noise margin nm C 30 % difference in v cm between any two channels | ? v cm |50mv difference in v od between any two channels | ? v od |100mv common-mode ac voltage (pk) without v cm cap termination ? v cm _ac 50 mv common-mode ac voltage (pk) with v cm cap termination ? v cm _ac 30 mv max overshoot peak |v od |v od _ac 1.3 x |v od |v max overshoot vdiff pk-pk v diff_pkpk 2.6 x |v od |v eye height v eye 1.4 x v od single-ended output impedance ro 35 50 70 ? output impedance mismatch ? ro 20 % ar0134_ds rev. g pub. 6/15 en 30 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor electrical specifications figure 16: differential output voltage for clock or data pairs notes: 1. one ui is defined as the normalized mean ti me between one edge and the following edge of the clock. 2. taken from 0v crossing point. 3. also defined with a maximum loading capacitance of 10pf on any pin. the loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3ui. 4. the absolute mean skew between the clock lane and any data lane in the same phy between any edges. 5. the absolute mean skew between any clock in one phy and any data lane in any other phy between any edges. 6. differential skew is defined as the skew between complementary outputs. it is measured as the absolute time between the two complementary edges at mean v cm point. table 17: rise and fall times measurement conditions: hispi powe r supply 0.4v, max freq 700 mhz parameter symbol min typ max unit data rate 1/ui 280 C 700 mb/s max setup time from transmitter txpre 0.3 C C ui 1 max hold time from transmitter txpost 0.3 C C ui rise time (20% - 80%) rise C 0.25ui C fall time (20% - 80%) fall 150ps 0.25 ui C clock duty pll_duty 45 50 55 % bitrate period t pw 1.43 3.57 ns 1 eye width t eye 0.3 ui 1, 2 data total jitter (pk pk)@1e-9 t totaljit 0.2 ui 1, 2 clock period jitter (rms) t ckjit 50 ps 2 clock cycle to cycle jitter (rms) t cyjit 100 ps 2 clock to data skew t chskew -0.1 0.1 ui 1, 2 phy-to-phy skew t |physkew| 2.1 ui 1, 5 mean differential skew t diffskew C100 100 ps 6 0v diff) vdiffmax vdiffmin output signal is 'cp - cn' or 'dp - dn' ar0134_ds rev. g pub. 6/15 en 31 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor electrical specifications figure 17: eye diagram for clock and data signals figure 18: skew within the phy and output channels clkjitter t rigger/ reference vdiff max vdiff ui/ 2 ui/ 2 vdiff txpre txpost clock mask data mask rise fall 20% 80% tcmpskew vcmd tc hskew1phy ar0134_ds rev. g pub. 6/15 en 32 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor power-on reset and standby timing power-on reset and standby timing power-up sequence the recommended power-up sequence for the ar0134 is shown in figure 19. the avail- able power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. turn on v dd _pll power supply. 2. after 0?10 ? s, turn on v aa and v aa _pix power supply. 3. after 0?10 ? s, turn on v dd _io power supply. 4. after the last power supply is stable, enable extclk. 5. if reset_bar is in a low state, hold reset_bar low for at least 1ms. if reset_bar is in a high state, assert reset_bar for at least 1ms. 6. wait 160000 extclks (for internal initialization into software standby). 7. configure pll, output, and image settings to desired values. 8. wait 1ms for the pll to lock. 9. set streaming mode (r0x301a[2] = 1). figure 19: power up notes: 1. xtal settling time is component-de pendent, usually taking about 10 C 100 ms. 2. hard reset time is the minimum time required after power rails are settled. in a circuit where hard reset is held down by rc circuit, then the rc ti me must include the all power rail settle time and xtal settle time. table 18: power-up sequence definition symbol minimum typical maximum unit v dd _pll to v aa /v aa _pix t0 0 10 C ? s v aa /v aa _pix to v dd _io t1 0 10 C ? s v dd _io to v dd t2 0 10 C ? s v dd to v dd _slvs t3 0 10 C ? s xtal settle time tx C 30 1 Cms hard reset t4 1 2 CC ms internal initializat ion t5 160000 C C extclks pll lock time t6 1 C C ms v dd _pll (2.8) v aa _pix v aa (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _slvs (0.4) extclk reset_bar t0 t1 t2 t3 tx t4 t5 t6 hard reset internal initialization software standby pll lock streaming ar0134_ds rev. g pub. 6/15 en 33 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor power-on reset and standby timing 3. it is critical that v dd _pll is not powered up after the other power supplies. it must be powered before or at least at the same time as the others. if the case happens that v dd _pll is powered after other supplies then the sensor may have functionalit y issues and will experience high current draw on this supply. power-down sequence the recommended power-down sequence for the ar0134 is shown in figure 20. the available power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. disable streaming if output is acti ve by setting standby r0x301a[2] = 0 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. turn off v dd _slvs. 4. turn off v dd . 5. turn off v dd _io 6. turn off v aa /v aa _pix. 7. turn off v dd _pll. figure 20: power down table 19: power-down sequence definition symbol minimum typical maximum unit v dd _slvs to v dd t0 0 C C ? s v dd to v dd _io t1 0 C C ? s v dd _io to v aa /v aa _pix t2 0 C C ? s v aa /v aa _pix to v dd _pll t3 0 C C ? s pwrdn until next pwrup time t4 100 C C ms v dd _io (1.8/2.8) t4 t 0 t1 t3 t2 extclk v dd _slvs (0.4) v dd (1.8) v aa _pix v aa (2.8) v dd _pll (2.8) power down until next power up cycle ar0134_ds rev. g pub. 6/15 en 34 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor power-on reset and standby timing note: t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged. standby sequence figures 21 and 22 show timing diagrams for entering and exiting standby. delays are shown indicating the last valid register write prior to entering standby as well as the first valid write upon exiting standby. also shown is timing if the extclk is to be disabled during standby. figure 21: enter standby timing figure 22: exit standby timing extclk standby fv 50 e xtc l ks r egister writes not valid registerwrites valid sdata 750 e xtc l ks extclk standby fv trigger 10 e xtc l ks 1ms 28 rows + c it r egis ter writes not valid r egis ter writes valid sdata ar0134_ds rev. g pub. 6/15 en 35 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor power-on reset and standby timing figure 23: quantum efficiency C monochrome sensor (typical) ar0134_ds rev. g pub. 6/15 en 36 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor power-on reset and standby timing figure 24: quantum efficiency C color sensor (typical) ar0134_ds rev. g pub. 6/15 en 37 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor power-on reset and standby timing table 20: chief ray angle - 25deg mono image height cra (%) (mm) (deg) 00 0 5 0.150 1.35 10 0.300 2.70 15 0.450 4.04 20 0.600 5.39 25 0.750 6.73 30 0.900 8.06 35 1.050 9.39 40 1.200 10.71 45 1.350 12.02 50 1.500 13.33 55 1.650 14.62 60 1.800 15.90 65 1.950 17.16 70 2.100 18.41 75 2.250 19.64 80 2.400 20.85 85 2.550 22.05 90 2.700 23.22 95 2.850 24.38 100 3000 25.51 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 102030405060708090100110 cra (deg) i h i ht (%) ar0134_ds rev. g pub. 6/15 en 38 ?semiconductor components industries, llc,2015 ar0134: 1/3-inch 1.2 mp cmos digital image sensor package dimensions package dimensions figure 25: 63-ball ibga package outline drawing notes: 1. dimensions in mm. dimensions in () are for reference only. encapsulant: epoxy. substrate material: plastic laminate 0.25 thickness. lid material: borosilicate glass 0.4 0.04 thickness. refractive index at 20c = 1.5255 @ 546nm and 1.5231 @ 588nm. double side ar coating: 530-570nm r< 1%; 420-700nm r < 2%. image sensor die: 0.2mm thickness. solder ball material: sac305 (95% sn, 3% ag, 0.5% cu). dimensions apply to sold er balls post reflow. pre-flow ball is0.5 on a ? 0.4 smd ball pad. maximum rotation of optical area relative to package edges: 1 . maximum tilt of optical area relative to substrate plane : 25 ? m. maximum tilt of cover glass relative to optical area plane : 50 ? m. 2 3 4 5 6 7 d e ar0134_ds rev. g pub. 6/15 en 39 ?semiconductor components industries, llc,2015 ar0134: 1/3-inch 1.2 mp cmos digital image sensor package dimensions figure 26: 48-pin ilcc package drawing notes: 1. dimensions in mm. dimensions in () are for reference only. encapsulant: epoxy. substrate material: plastic laminate 0.5 thickness. lid material: borosilicate glass 0.4 0.04 thickness. refractive index at 20c = 1.5255 @ 546nm and 1.5231 @ 588nm. double side ar coating: 530-570nm r< 1%; 420-700nm r < 2%. lead finish: gold plating, 0.5 microns minimum thickness. image sensor die: 0.2mm thickness. maximum rotation of optical area relative to package edges: 1 . maximum tilt of optical area relative to substrate plane : 25 ? m. maximum tilt of cover glass relative to optical area plane : 50 ? m. 2 3 4 5 6 7 d e ar0134_ds rev. g pub. 6/15 en 40 ?semiconductor components industries, llc,2015. ar0134: 1/3-inch 1.2 mp cmos digital image sensor revision history revision history rev. g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/9/15 ? updated ?ordering information? on page 2 rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/29/15 ? updated ?ordering information? on page 2 ? removed confidential marking rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/19/14 ? updated to on semiconductor template rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/13/14 ? updated table 1, ?key parameters,? on page 1 ? updated figure 4: ?typical configuratio n: serial four-lane hispi interface,? on page 10 ? updated figure 6: ?9x9mm 63-ball ibga package,? on page 12 ? updated table 5, ?two-wire serial bus characteristics,? on page 22 ? updated table 6, ?i/o timing charac teristics, parallel output (1.8v v dd _io) 1 ,? on page 24 ? updated table 7, ?i/o timing charac teristics, parallel output (2.8v v dd _io) 1 ,? on page 25 ? updated ?two-wire serial register interface? on page 17 ? split table 6 and updated values in table 8, ?i/o rise slew rate (2.8v v dd _io) 1 ,? on page 26 and table 9, ?i/o fall slew rate (2.8v v dd _io) 1 ,? on page 26 ? updated ?power-up sequence? on page 32 ? updated figure 19: ?power up,? on page 32 ? updated figure 25: ?63-ball ibga package outline drawing,? on page 38 ? updated figure 26: ?48-pin ilcc package drawing,? on page 39 rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/13/13 ? updated to production ? applied updated aptina template ? updated ?general description? on page 1 ? updated table 1, ?key parameters,? on page 1 ? updated table 3, ?available part numbers,? on page 3 ? updated ?features overview? on page 7 ? added ?pixel data format? on page 8 ? updated table 6, ?i/o timing charac teristics, parallel output (1.8v v dd _io) 1 ,? on page 24 ? updated table 7, ?i/o rise slew rate (2.8v vdd_io)1,? on page 23 ? updated table 8, ?i/o fall slew rate (2.8v vdd_io)1,? on page 23 ? updated table 9, ?i/o rise slew rate (1.8v vdd_io)1,? on page 23 ? added ?two-wire serial register interface? on page 17 ? added ?standby sequence? on page 34 ? added table 20, ?chief ray angle - 25deg mono,? on page 37 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/23/13 ? updated to preliminary ? updated ?features? on page 1 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. ar0134: 1/3-inch 1.2 mp cmos digital image sensor revision history ar0134_ds rev. g pub. 6/15 en 41 ?semiconductor components industries, llc,2015 . ? updated third paragraph of ?general description? on page 6 ? updated figure 15: ?i/o timing diagram,? on page 24 ? updated table 6, ?i/o timing charac teristics, parallel output (1.8v v dd _io) 1 ,? on page 24 ? added figure 21: ?enter standby timing,? on page 34 ? added figure 22: ?exit standby timing,? on page 34 ? added table 7, ?i/o rise slew rate (2.8v vdd_io)1,? on page 23 ? added table 8, ?i/o fall slew ra te (2.8v vdd_io)1,? on page 23 ? added table 9, ?i/o rise slew rate (1.8v vdd_io)1,? on page 23 ? added table 10, ?i/o fall slew rate (1.8v vdd_io)1,? on page 24 ? updated ?power-up sequence? on page 32 ? updated table 18, ?power-up sequence,? on page 32 ? added figure 21: ?enter standby timing,? on page 34 ? added figure 22: ?exit standby timing,? on page 34 ? added figure 23: ?quantum efficiency ? monochrome sensor (typical),? on page 35 rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9/19/12 ?initial release |
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